1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
Portable electronics devices such as a cellular phone, a personal digital assistance (PDA), and a digital still camera have become increasingly sophisticated in functionality. Under the circumstance, these products must be compact and lightweight in order to be accepted in the market, and a highly integrated system LSI is required for implementing such products. On the other hand, there has been a demand for electronics devices which are easier to use and more convenient, and thus higher functionality and higher performance have been required for the LSI employed in these devices. Therefore, on the one hand, the number of I/Os increases as the degree of integration increases in the LSI chip, but, on the other hand, there is a strong requirement for making the package itself more compact. In order to meet these requirements at the same time, the development of a semiconductor package suitable for mounting semiconductor components on a substrate with high density is strongly demanded. In order to address these demands, various packaging techniques referred to as a chip size package (CSP) have been developed.
A ball grid array (BGA) is an example of such a package. In the BGA, first a semiconductor chip is mounted on a substrate for packaging. After the semiconductor chip is resin-molded, solder balls serving as external terminals are formed in an array on the surface opposite to the resin-molded surface. Since a mounting area is obtained as a plane in the BGA, the size reduction of the package can be relatively easily attained. In addition, a circuit board is not required to be fine-pitch compatible, and a high accuracy mounting technique is also not required. Therefore, by employing the BGA, the total mounting cost can be reduced even when the packaging cost is somewhat expensive.
In such a package, transfer molding, injection molding, potting, dipping, or the like has been employed for sealing a semiconductor chip (see, for example, Japanese Patent Laid-Open Publication No. Hei 8-162486).
In addition, in order to implement a slim type LSI system with higher accuracy and higher functionality, a technique has been disclosed (see, for example, Japanese Patent Laid-Open Publication No. 2002-94247) in which a layer containing passive elements is formed in the upper portion of a base substrate by thin film technology and thick film technology, the passive elements including resistors, capacitors, and pattern wiring portions receiving power or a signal from the base substrate side via a dielectric insulating layer.